
#include "hal_spi.h"


static spi_config_t dspi_config[5];

void hal_spi_init(spi_controller_t channel ,uint32_t hz ,spi_pcs_polarity_t cs_level ,spi_mode_en mode ,enabled_en en)
{
	SPIDriver * pspi = NULL;
	dspi_config[channel].WhichSpiController = channel;			
	dspi_config[channel].bitsPerSec = hz;			
	dspi_config[channel].pcsPolarity = cs_level;
	dspi_config[channel].bitcount = 8;
	
	if((SPI_CPOL0_CPHA0 == mode) ||(SPI_CPOL1_CPHA0 == mode))
	{
		dspi_config[channel].clkPhase = SPI_CLOCK_PHASE_1ST_EDGE;
	}else if((SPI_CPOL0_CPHA1 == mode)||(SPI_CPOL1_CPHA1 == mode))
	{
		dspi_config[channel].clkPhase = SPI_CLOCK_PHASE_2ND_EDGE;
	}
	else
	{
		dspi_config[channel].clkPhase = SPI_CLOCK_PHASE_1ST_EDGE;
	}
	
	if((SPI_CPOL0_CPHA0 == mode) || (SPI_CPOL0_CPHA1 == mode))
	{
		dspi_config[channel].clkPhase = SPI_ACTIVE_LOW;
	}
	else if((SPI_CPOL1_CPHA0) == mode || (SPI_CPOL1_CPHA1) == mode)
	{
		dspi_config[channel].clkPhase = SPI_ACTIVE_HIGH;
	}
	else
	{
		dspi_config[channel].clkPhase = SPI_ACTIVE_LOW;
	}
	
	dspi_config[channel].isClkContinuous = FALSE;
	
	if((dspi_config[channel].lsbFirst != TRUE) ||(dspi_config[channel].lsbFirst != FALSE))
	{
		dspi_config[channel].lsbFirst = FALSE;
	}
	
	dspi_config[channel].transferType = SPI_USING_POLLING;// SPI_USING_INTERRUPTS
	dspi_config[channel].dmaType = DSPI_DMA_NONE;
	dspi_config[channel].callback = NULL;
	dspi_config[channel].continuousPCS = TRUE;
	dspi_config[channel].whichPCS = 0;
	
	switch(channel)
	{
	case DSPI0:
		pspi = &SPID1;
		break;
	case DSPI1:
		pspi = &SPID2;
		break;
	case DSPI2:
		pspi = &SPID3;
		break;
	case DSPI3:
		pspi = &SPID4;
		break;
	case DSPI4:
		pspi = &SPID5;
		break;
	default:
		break;
	}
	SPI_LLD_Init(pspi,&dspi_config[channel],SPI_MASTER);
	hal_spi_enabled(channel,en);
}

result_en hal_spi_write(spi_controller_t channel ,const uint8_t *send_buff ,uint8_t * rece_buff)
{
	SPIDriver * pspi = NULL;
	result_en result = SPI_FAIL;
	switch(channel)
	{
	case DSPI0:
		pspi = &SPID1;
		result = SPI_SUCCEE;
		break;
	case DSPI1:
		pspi = &SPID2;
		result = SPI_SUCCEE;
		break;
	case DSPI2:
		pspi = &SPID3;
		result = SPI_SUCCEE;
		break;
	case DSPI3:
		pspi = &SPID4;
		result = SPI_SUCCEE;
		break;
	case DSPI4:
		pspi = &SPID5;
		result = SPI_SUCCEE;
		break;
	default:
		result = SPI_FAIL;
		break;
	}
	SPI_LLD_Exchange(pspi , 1 ,(uint8_t *)send_buff ,rece_buff);
	return result;
}

result_en hal_spi_writes(spi_controller_t channel ,const uint8_t *send_buff ,uint8_t * rece_buff ,uint16_t len)
{
	SPIDriver * pspi = NULL;
	result_en result = SPI_FAIL;
	switch(channel)
	{
	case DSPI0:
		pspi = &SPID1;
		result = SPI_SUCCEE;
		break;
	case DSPI1:
		pspi = &SPID2;
		result = SPI_SUCCEE;
		break;
	case DSPI2:
		pspi = &SPID3;
		result = SPI_SUCCEE;
		break;
	case DSPI3:
		pspi = &SPID4;
		result = SPI_SUCCEE;
		break;
	case DSPI4:
		pspi = &SPID5;
		result = SPI_SUCCEE;
		break;
	default:
		result = SPI_FAIL;
		break;
	}
	SPI_LLD_Exchange(pspi , len ,(uint8_t *)send_buff ,rece_buff);
	return result;
}

void hal_spi_enabled(spi_controller_t channel ,enabled_en en)
{
	SPIDriver * pspi = NULL;
	switch(channel)
	{
	case DSPI0:
		pspi = &SPID1;
		break;
	case DSPI1:
		pspi = &SPID2;
		break;
	case DSPI2:
		pspi = &SPID3;
		break;
	case DSPI3:
		pspi = &SPID4;
		break;
	case DSPI4:
		pspi = &SPID5;
		break;
	default:
		pspi = NULL;
		break;
	}
	
	if(pspi != NULL)
	{
		if(SPI_ENABLE == en)
		{
			pspi->dspi->MCR.B.MDIS = 0u;
		}else if(SPI_DISABLE == en)
		{
			pspi->dspi->MCR.B.MDIS = 1u;
		}
		else
		{
			
		}
	}
	else
	{
		
	}
}


/*
void hal_spi_role(spi_controller_t channel ,spi_functional_mode_t role)
{
	
}

spi_functional_mode_t hal_spi_get_role(spi_controller_t channel)
{
	
}
*/
